Parallel data transmission unit using byte error correcting code

Details Parallel data transmission unit using byte error correcting code Parallel data transmission unit using byte error correcting code

1995-03-29

1997-11-11

Baker, Stephen M.

Excavating

371 381, H03M 1322

Patent

active

056871813

ABSTRACT:
A parallel signal of a k bit width is converted such that every m bits of width is made a byte. It is then coded by a plurality i of encoders into a t byte error correcting code in which a byte length is of m bits and a code length is of 1 bytes. The coded parallel signal is interleaved by an interleaver and is distributed into a plurality 1 of transmitters. Each transmitter converts the parallel signal of an mi bit width into a serial signal and transmits the converted signal. Each receiver converts the received serial signal into a parallel signal of an mi bit width and outputs the signal thus converted. The signals outputted from a plurality i of receivers are deinterleaved by a de-interleaver, and the deinterleaved signals are inputted to a plurality i of decoders. The decoders carry out correction of a t byte error in which one byte is of m bits, and integrates the signals outputted therefrom and outputs a parallel signal of a k bit width. By making use of the byte error correcting code, the interleaver, and the deinterleaver, the parallel data transmission unit provides for the correction of a byte error having a byte length longer than that of the code, and also provides for the reduction in scale of the encoders and decoders. Each of i, k, l, and m is an integer not less than 2.

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"Fibre Channel -Physical and signaling interface (FC-PH)", FC-PH REV 4.1, Aug. 12, 1993, pp. 1-96.
S. Kaneda, "Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems", IEEE Transactions on Computers, vol. C-31, No. 7, Jul. 1982.
M. Y. Hsiao, "A Class of Optimal Minimum Odd-weight-column SEC-DED Codes", SEC-DED Codes, Jul. 1970, pp. 395-401.
A.K. Bhatt, "A High-Speed Parallel Encoder/Decoder For b-Adjacent Error-Checking Codes", 3rd USA-JAPAN Computer Conference 1978, pp. 203-207 .

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