Parallel data output control circuit and semiconductor device

Details Parallel data output control circuit and semiconductor device Parallel data output control circuit and semiconductor device

2011-07-12

2011-07-12

Jeanglaude, Jean B (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Converter is part of control loop

C341S100000, C341S101000

Reexamination Certificate

active

07978108

ABSTRACT:
A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

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