Parallel data bus integrated clocking and control

Details Parallel data bus integrated clocking and control Parallel data bus integrated clocking and control

1997-12-31

2001-07-17

Chin, Wellington (Department: 2664)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C375S354000

Reexamination Certificate

active

06262998

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to data transmission, and more particularly to high-speed data bus having integrated clock and control signal information carried by a single channel.
High-speed data communication systems having a need for improved maintenance of primary clock timing and synchronization of data carried by high-speed data buses.
DESCRIPTION OF THE RELATED ART
In high-speed data communications, in which the duration of data bits is of the same order or smaller than uncertainties in their propagation time, it is necessary to generate a clock signal that is synchronized to the data, in order to accurately regenerate the bit stream at the receiving end of each data link. When serial data paths are involved, a separate clock path running parallel to the data path is usually considered to be excessive in overhead. It is more common to increase the data rate of the serial data path by 12% to 25%, for example, so that the original bit stream can be encoded to provide an increased and guaranteed-minimum number of transitions to which a clock signal can be reliably phase-locked. The phase-locked loop (PLL) needed for such clock signal generation is complicated by the need to handle a randomly variable number of missing transitions while remaining immune to locking at fractional ratios of the bit frequency.
For parallel data signal paths, which are employed to further increase data rate, a parallel clock path usually represents the last overhead because this arrangement simplifies clock signal regeneration and the clock information is shared by all of the parallel data signals, each of which can carry data at its full bit rate without any data encoding. It may often be necessary, however, to provide means to individually adjust the phase of each data path relative to the clock signal in order to correct for signal path differences among the data paths, such as different wiring lengths or different interface delays. When there are several data sources, in order to control individual phase settings of this type in a cooperative manner, it is necessary to provide a control data channel that is separate from the data signals to be controlled. In addition to such control data, it is often required to carry lower data-rate information, such as framing information. The parallel data bus may carry multiplexed data requiring de-multiplexing with re-synchronization.
Thus, in both serial and parallel data transmissions, there is often a need to transmit both synchronous clock signals and control data, and there is often a need for synchronizing multiplexed data carried on a high-speed data bus.
Problems Solved by the Invention
With respect to high-speed data buses, the use of multiple signal paths for synchronous clocks, control data, and framing data has added cost to data transmission equipment. In some cases, it has been necessary to increase data rates in order to transmit control and clock synchronizing information, thus further increasing cost. These shortcomings of the background art may be avoided by use of the present invention.
Purposes, Objects, and Advantages of the Invention
The purpose of the invention is a more efficient high-speed parallel data bus having a single integrated signal path carrying both synchronous clock information and control data. A general object of the invention is enabling a high-speed parallel data bus to be implemented in a more compact and flexible manner than heretofore, while achieving the maximum speed capability and/or maximum margins for a given speed requirement. Another object is an improved re-synchronization of multiplexed data. Overall objects include reducing costs and risks in development of high-speed data buses. Finally, an important object is providing an efficient means of achieving both a synchronous clock and a control data channel integrated in a single signal path used with a high-speed parallel data bus.
SUMMARY OF THE INVENTION
A clock is always needed with transmitted data in order to define the position of individual bits in the data sequences. If the clock is directly transmitted, such a clock signal may require special handling, e.g., the use of higher-speed interfaces than those used by the data channels. In this invention the clock signal is transmitted at a lower rate, and only a primary edge (for example, the falling edge) is used to control the timing of a PLL or DLL, which can then regenerate all required equal- or higher-rate clocks with required stability and phase relations. By using only timing increments of one bit time for the clock signal high and low periods, the same transmission media and interfaces may be used for the clock as are normally used for the associated data stream or streams. Furthermore, the alternate edge of the signal is independently modulated in increments of one data bit time to carry control data. Control data transmitted in this way, integrated with the clock signal, may be used for any purpose, including specific low-speed timing purposes often called framing. At the same time, and in the same manner, such control data can be used in a process of adjusting or “trimming” delays of data from two or more sources multiplexed onto a data line. At the receiving end of the bus, the delays are adjusted in accordance with the control data, so that the various multiplexed data streams will align with each other in time at data receivers used to recover the bit streams. One clock signal may be used in these ways for many parallel data lines, which may differ from one another, and which may also require unique timing settings. The clock signal is an ideal signal to carry such control data, since it must already connect to all transmitters and receivers, and because it directly provides the timing information needed to optimally recover the data it carries.
Thus, a data bus is provided having both a synchronous clock and a channel of data control information integrated in a single signal path. For a data bus having a particular bit time, the integrated clock and control signal has clock signal high and low time in units equal to one bit time. One edge of the integrated clock and control signal is fixed in phase for bit timing, the alternate edge is phase-modulated. The phase-modulated clock edge carries framing and control data. The fixed-phase bit-timing edge regulates a DLL or PLL to extend the timing. The clock rate is preferably chosen to be equal to the multiplexing cycle rate of multiplexed data carried on the parallel bus.


REFERENCES:
patent: 3925762 (1975-12-01), Heitlinger et al.
patent: 4972161 (1990-11-01), Davies et al.
patent: 5140611 (1992-08-01), Jones et al.
patent: 5568526 (1996-10-01), Ferraiolo et al.

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