Parallel counter and application to binary adders

Details Parallel counter and application to binary adders Parallel counter and application to binary adders

1982-04-30

1984-12-11

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

044882530

ABSTRACT:
A counter comprising MOS transistor cells providing a tree like network. The logic value 1 is shifted to the left (bits of highest weight or rank) as many times as there are input binary variables with the logic value 1. The corresponding output is then at level 1 and all the other outputs are at logic level 0. An adder is obtained by providing a NOR gate decoding arrangement connected to the outputs of the counter.

REFERENCES:
patent: 3603776 (1971-09-01), Weinberger
patent: 3636334 (1972-01-01), Sroboda
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 4189716 (1980-02-01), Krambeck
Singh et al., "Multiple Operand Addition and Multiplication" IEEE Trans. on Computers, vol. C-22, No. 2, Feb. 1973, pp. 113-120.

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