Parallel counter and a logic circuit for performing...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07136888

ABSTRACT:
A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

REFERENCES:
patent: 3634658 (1972-01-01), Brown
patent: 3757098 (1973-09-01), Wright
patent: 4399517 (1983-08-01), Niehaus et al.
patent: 4607176 (1986-08-01), Burrows et al.
patent: 5095457 (1992-03-01), Jeong
patent: 5095547 (1992-03-01), Kerns
patent: 5175862 (1992-12-01), Phelps et al.
patent: 5187679 (1993-02-01), Vassiliadis et al.
patent: 5325320 (1994-06-01), Chiu
patent: 5343417 (1994-08-01), Flora
patent: 5497342 (1996-03-01), Mou et al.
patent: 5524082 (1996-06-01), Horstmann et al.
patent: 5701504 (1997-12-01), Timko
patent: 5964827 (1999-10-01), Ngo et al.
patent: 5995029 (1999-11-01), Ryu
patent: 6008668 (1999-12-01), Saruwatari
patent: 6023566 (2000-02-01), Belkhale et al.
patent: 6175852 (2001-01-01), Dhong et al.
patent: 6269386 (2001-07-01), Siers et al.
patent: 6344760 (2002-02-01), Pyo
patent: 6445210 (2002-09-01), Nojiri
patent: 6490608 (2002-12-01), Zhu
patent: 6577164 (2003-06-01), Tomita
patent: 6724223 (2004-04-01), Ichiguchi et al.
patent: 6882175 (2005-04-01), Motegi et al.
patent: 6883011 (2005-04-01), Rumynin et al.
patent: 6938061 (2005-08-01), Rumynin et al.
patent: 2003/0016055 (2003-01-01), Oodaira et al.
patent: 2004/0103135 (2004-05-01), Talwar
patent: 2004/0153490 (2004-08-01), Talwar et al.
patent: 2005/0021585 (2005-01-01), Rumynin et al.
patent: 0168650 (1986-01-01), None
patent: 0309292 (1989-03-01), None
patent: 0442356 (1991-08-01), None
patent: 0741354 (1996-11-01), None
patent: 2475250 (1981-08-01), None
patent: 2016181 (1979-09-01), None
patent: 2062310 (1981-05-01), None
patent: 2365636 (2002-02-01), None
patent: 2365637 (2002-02-01), None
patent: WO-99/22292 (1999-05-01), None
patent: WO-02/12995 (2002-02-01), None
Nicholson, J. O., “Parallel-Carry Adders Listing Two-Bit Covers”,IBM Technical Disclosure Bulletin, 22(11), (Apr., 1980),5036-5037.
Ong, S., et al., “A Comparision of ALU Structures for VLSI Technology”,Proceedings, 6th Symposium on Computer Arithmetic(IEEE), (1983),10-16.
Schmookler, M. S., et al., “Group-Carry Generator”,IBM Technical Disclosure Bulletin, 6(1), (Jun., 1963),77-78.
Weinberger, A., “Extension of the Size of Group Carry Signals”,IBM Technical Disclosure Bulletin, 22(4), (Sep., 1979),1548-1550.
Weinberger, A., “Improved Carry-Look-Ahead”,IBM Technical Disclosure Bulletin, 21(6), (Nov., 1978),2460-2461.
Booth, Andrew, “A Signed Binary Multiplication Technique”,Oxford University Press, Reprinted from Q.J. Mech. Appl. Math. 4:236-240, (1951), pp. 100-104.
Chakraborty, S., et al., “Synthesis of Symmetric Functions for Path-Delay Fault Testability”,12th International Conference on VLSI Design, (1999), pp. 512-517.
Dadda, L., “On Parallel Digital Multipliers”,Associazione Elettrontecnia ed Elettronica Italiana, Reprinted from Alta Freq. 45:574-580, (1976), pp. 126-132.
Dadda, L., “Some Schemes For Parallel Multipliers”,Assocciazione Elettrotenica ed Elettronica Italiana, Reprinted from Alta Freq. 34:349-356, (1965), pp. 118-125.
Debnath, D., “Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing”,IEICE Trans. Inf.&Syst., vol. E80-D, No. 10, (1997), pp. 1001-1008.
Drechsler, R., et al., “Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions”,IEEE, (1995), pp. 91-97.
Drechsler, R., et al., “Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions”,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 1, (1997), pp. 1-5.
Fleisher, H., “Combinatorial Techniques for Performing Arithmetic and Logical Operations”,IBM Research Center, RC-289, Research Report, (Jul. 18, 1960), pp. 1-20.
Foster, Caxton, et al., “Counting Responders in an Associative Memory”,The Institute of Electrical and Electronics Engineers, Inc., Reprinted, with permission, from IEEE Trans. Comput. C-20:1580-1583, (1971), pp. 86-89.
Ho, I., et al., “Multiple Addition by Residue Threshold Functions and Their Representation By Array Logic”,The Institute of Electrical and Electronics Engineers, Inc., Reprinted, with permission from IEEE Trans. Comput. C-22: 762-767, (1973), pp. 80-85.
Jones, Robert, et al., “Parallel Counter Implementation”,IEEE, (1992), pp. 381-385.
Nienhaus, H., “Efficient Multiplexer Realizations of Symmetric Functions”,IEEE, (1981), pp. 522-525.
Oklobdzija, V.G., et al., “Improving Multiplier Design by Using Improved Column Compression Tree and Optimized Final Adder in CMOS Technology”,IEEE Transactions on Very Large Scale Integration(VLSI)Systems, vol. 3, No. 2, (1995), pp. 292-301.
Swartzlander, Jr., Earle, “Parallel Counters”,Institute of Electrical and Electronic Engineers, Inc., Reprinted, with permission from IEEE Trans. Comput. C-22:1021-1024, (1973), pp. 90-93.
Vassiliadis, S., et al., “7/2 Counters and Multiplication with Threshold Logic”,IEEE, (1997), pp. 192-196.
Wallace, C., “A Suggestion for a Fast Multiplier”,IEEE Transactions on Electronic Computers, (1964), pp. 14-17.
Zuras, D, et al., “Balanced Delay Trees and Combinatorial Division in VLSI”,IEEE Journal of Solid State Circuits, SC-21, IEEE Inc, New York, vol. SC-21, No. 5, (1986), pp. 814-819.
Goto, et al., “A 54 x 54-b Regularly Structured Tree Multiplier”,IEEE Journal of Solid-State Circuits, vol. 27, No. 9, (Sep. 1992), 1229-1236.
Hekstra, et al., “A Fast Parallel Multiplier Architecture”,IEEE International Symposium on Circuits and Systems; Institute of Electrical and Electronic Engineers, c1977-c1996, 20v. :28cm, (1992),2128-2131.
Bedrij, O. J., “Carry-Select Adder”,IRE Trans., EC-11, (Jun. 1962),340-346.
Knowles, S., “A Family of Adders”,Proc. 14th IEEE Symp. on Computer Arithmetic, (1990),30-34.
Kogge, P. M., et al., “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations”,IEEE Trans. Computers, vol. C-22, No. 8, (Aug. 1973),786-793.
Ladner, Richard E., et al., “Parallel Prefix Computation”,Journal of ACM, vol. 27, No. 4, (Oct. 1980),831-838.
Ling, Huey, “High-Speed Binary Adder”,IBM Journal of Research and Development, vol. 25, No. 3, (1981),156-166.
Sklansky, J., “Conditional-Sum Addition Logic”,IRE Trans., EC-9, (Jun. 1960),226-231.
Weinberger, A., et al., “A Logic for High-Speed Addition”,Nat. Bur. Stand. Circ., 591, (1958),3-12.
“Communication Pursuant to Article 96(2) EPC, for application No. EP 02 722 402.1, date mailed Jun. 6, 2005”, 3 pages.
Song, Paul, J., et al., “Circuit and Architecture Trade-offs for High-Speed Multiplication”,IEEE Journal of Solid-State Circuits, vol. 26, No. 9,(Sep. 1991),1184-1198.

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