Patent
1996-05-02
1997-07-15
Black, Thomas G.
39520001, 39520003, 395311, 395505, 395511, 395739, 395851, 395858, 395868, G06F 15163, G06F 1700
Patent
active
056491069
ABSTRACT:
A parallel computer having a plurality of cluster buses 2 which are connected to the processor (PE) 1 via the selectors 6. The selectors 6 maintain the same condition until the next instruction is received. In this system, the clusters 11 are reconstructed at appropriate timing during the operation of the processor, thus allowing the number of processors PEs in a cluster to be exchanged in response to variation in the process load allocated to each cluster 11. Accordingly, the resources of the computer are used more effectively. The execution environment of each process may be independent. Real time execution of each process can be assured.
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Parallel Circuit Simulation Machine Cenju Information Processing, vol. 31, No. 5, May, 1990.
Ward et al., Computation Structures, Preface, pp. 559-577, 1990.
Kondo Michimasa
Tsujimichi Shingo
Black Thomas G.
Homere Jean R.
Mitsubishi Denki & Kabushiki Kaisha
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