Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1996-12-06
1999-07-27
Barry, Esq., Lance Leonard
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
39580013, 712 13, G06F 1300
Patent
active
059283513
ABSTRACT:
A parallel computer system capable of arbitrarily selecting nodes participating in barrier synchronization while enabling an arbitrary number of node groups to independently execute a process requiring the barrier synchronization. A communication network for the parallel computer system includes a plurality of routing controllers. Each routing controller has a register for setting a predetermined number of receipts of barrier synchronization request messages from other routing controllers, a destination to which the barrier synchronization request message is transmitted, and a destination to which a barrier synchronization establishment message is transmitted. If a destination of transmission of the barrier synchronization request message is set when completing a predetermined number of receipts of the barrier synchronization request messages and receipts of a barrier synchronization request message from a self-node, the barrier synchronization request message is transmitted to that destination of transmission. If the transmission destination is not set, the barrier synchronization establishment message is transmitted to the set transmission destination of the barrier synchronization establishment message. When receiving the barrier synchronization establishment message, the barrier synchronization establishment message is also transmitted to the set transmission destination of the barrier synchronization establishment message.
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Horie Takeshi
Kobayashi Ken-ichi
Nagatsuka Masaaki
Shiraki Osamu
Barry, Esq. Lance Leonard
Fujitsu Ltd.
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