Parallel computer comprised of processor elements having a local

Details Parallel computer comprised of processor elements having a local Parallel computer comprised of processor elements having a local

1989-01-27

1994-03-22

Shaw, Gareth O.

Boots, shoes, and leggings

395800, 364DIG1, 364228, 3642283, 364284, 364260, G06F 1300

Patent

active

052972550

ABSTRACT:
In a parallel computer, there are provided a plurality of processor elements 1-1 to 1-n) connected to each other by a network (2); each of said processor elements including a local memory (6) for holding a program and data related thereto, a processor (3) for performing an instruction in said program, a circuit (5) for transferring the data to the other processor elements, and a circuit (4) for receiving the data sent from the other processor element; a memory area (92:8) constructed of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and a memory (92,8) constructed of a plurality of tag areas, provided for each of the reception data areas, for storing a valid data tag or an invalid data tag indicating that the data in the corresponding reception data area is valid or invalid; a transmitting circuit (5) for transmitting the data to be transmitted with attaching a data identifier predetermined by said data; a receiving circuit for writing the data into one of said plurality of reception data areas in response to the data received from said network, and writing the valid data tag into one of said plurality of reception data areas, said receiving circuit being parallel-operated with said processor; and, an access circuit (38) for reading both the data and tag from one of the reception data areas determined by said data identifier and from the corresponding tag areas in response to the data identifier designated by the instruction which is produced from said program for requiring the data reception, and for repeatedly reading the tag and data from the tag area and reception data area until the valid data tag is read out from the tag area in case that the read tag corresponds to the invalid data tag.

REFERENCES:
patent: 4780810 (1988-10-01), Torii et al.
patent: 4831512 (1989-05-01), Nakai et al.
patent: 4951193 (1990-08-01), Muramatsu et al.
Burton J. Smith, "Architecture and Applications of the HEP Multiprocessor Computer System", Society of Photo-Optical Instrumentation Engineers Real-Time Signal Processisng IV, vol. 298, Aug. 1981, pp. 241-248.
E. J. Lerner, "Data-Flow Architecture", IEEE Spectrum, vol. 21, No. 4, Apr. 1984, pp. 57-61.

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