Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-09-03
2004-03-30
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030
Reexamination Certificate
active
06714457
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor flash memory, and more particularly to programming multiple level cell (MLC) flash memory, including NAND and NOR type arrays.
2. Description of the Related Art
Flash memory is widely used in today's electronic products especially for portable applications as a result of its non-volatility and in system re-programmability. The basic structure of a flash memory cell contains a control gate, a drain diffusion region and a source diffusion region on the substrate to form a transistor with a floating gate under the control gate to be the electron storage device. The channel region lies under the floating gate with a tunnel oxide layer between the channel and floating gate that is the insulation layer. The energy barrier of the tunnel oxide can be overcome by applying a sufficiently high electric field across the tunnel oxide. This allows electrons to pass through the tunnel oxide, which is used to change the number of electrons stored in the floating gate. The number of electrons stored in the floating gate determines the threshold voltage (Vt) of the cell. More electrons stored in the floating gate causes the cell to have a higher Vt. The Vt of a cell is used to represent the stored data of the cell.
To change the Vt of a cell to a higher or lower value, the number of the electrons stored in the floating gate is increased or decreased by applying proper voltages to the control gate, the drain and source regions, and the channel region to cause electrons to move between one or more of these nodes and through the tunnel oxide layer to the floating gate. When the electrons are moved between the channel region and the floating gate, it is referred to as a channel operation. When the electrons are moved between the drain or source region and the floating gate, it is referred as an edge operation since it takes place on the overlap region between the edge of the floating gate and the drain or source region.
When changing the Vt of a flash memory cell, two operations are required. The first operation, called an erase operation, is applied to a large number of cells called a block. The second operation, called a program operation, is applied to a smaller number of cells called a page. The erase operation will change the Vt of all the cells in a selected block to a high Vt or a low Vt, depending on the design consideration. The program operation will change the Vt of selected cells to a value opposite that of the erase operation. While the erase operation is performed on a collective basis, the program operation must be bit selectable in order to change the Vt of a individual cell according to the desired data. There are various mechanisms and technologies suitable for erasing and programming different types of flash memories including the Fowler-Nordheim (F-N) tunneling mechanism, which is chosen because of its extremely low power consumption.
In U.S. Pat. No. 5,748,538 (Lee et al.) a flash memory cell array is directed to the use of Fowler-Nordheim tunneling for programming the cells. The memory cell stores two levels of threshold voltage (Vt). Both over erase and over programming repair capability is discussed. U.S. Pat. No. 5,768,188 (Park et al.) is directed to a multi-level flash memory cell (MLC) array using a conventional MLC programming scheme that uses a serial stepwise word line voltage to control the programming time as well as the Vt distribution of MLC.
A flash memory, which stores two levels of Vt in a cell, is called a single bit cell. For example, assume the low Vt level of a cell is below +2V and the high Vt level is above +4V. During a read operation, a voltage between the two Vt levels, e.g. +3V, is applied to the selected word line and in turn to the control gate of the selected cell to check the Vt of the cell. If the cell is in a low Vt state, the voltage applied to the control gate will turn on the channel of the selected cell and allow current to flow through the channel from the drain to the source. If the cell is in a high Vt state, the voltage applied to the control gate will not be able to turn on the channel of the cell, thus preventing current flowing from drain to source. With the source region grounded, the selected bit line and the drain region of the selected cell is biased at around +1V. A sense amplifier is used to detect the current flowing on the bit line and converts the amount of current flow into logical “0” or logical “1” data.
A Multiple Level Cell (MLC) technology has attracted a lot of attention due to its cost efficiency. By storing 2
N
discrete levels of Vt, the MLC can store N bits of data per cell, thus reducing the equivalent cell size to 1/N. Because of the multiple bits of data per cell, the MLC has become one of the best candidates in mass storage applications that typically require high density such as 512 Mb and beyond.
FIG. 1
shows an example of typical Vt distribution of 4-level MLC. The Vt of the cell is divided into four levels to represent data (
00
), (
01
), (
10
) and (
11
). When read, three reference voltages Vref
1
, Vref
2
and Vref
3
are applied to check the Vt level.
The implementation of MLC requires a key design technique, which is how to accurately control the Vt distribution of the programmed cell. Because the Vt distribution for each level and the margin between the levels is much smaller than that of the single bit cell, a highly accurate programming scheme is needed to achieve the tight Vt control. The conventional programming scheme used for single bit cell is not suitable for this purpose. When programming a single bit cell, typically the word line and bit line are coupled to fixed voltages. For example, the word line is coupled to +17V and the bit line is coupled to +0V. This voltage condition will cause the Vt of the programmed cell to increase. The final programmed Vt is controlled by the programming time. However, it is very difficult to achieve the tight Vt distribution requirement of MLC by using this approach.
FIG. 2
shows a typical curve of programmed Vt vs programming time. As the figure shows, the relationship between the programmed Vt and programming time is approximately an exponential curve; a higher Vt requires several orders longer time to program than the lower Vt. For example, programming Vt to +3.5V takes 200 us, the same program condition to program the Vt to +0.5V will take about only {fraction (1/1000)} of the time, or 200 ns. The extremely short programming time is very difficult to control and can easily end up being over programming. On the other hand, if the word line voltage is reduced to +11V to slow down the programming time for Vt so that +0.5V takes 200 us, the programming time for +3.5V will become as long as 200 ms.
FIG. 3A
shows a stepwise word line voltage to control the programming time and Vt distribution of an MLC.
FIG. 3B
shows the voltage setup for the word line and bit lines. Assuming four cells, M
1
, M
2
, M
3
and M
4
are selectively programmed to a Vt of +0.5V, +1.5V, +2.5V and +3.5V, respectively. The program operation is divided into four sequential steps. In the first step, the word line voltage is coupled to a voltage of +11V, and the bit lines of all the four cells, VBL
00
, VBL
01
, VBL
10
and VBL
11
, are coupled to 0V. The voltages of the source lines VSL
00
, VSL
01
, VSL
10
and VSL
11
can be either coupled to the same voltage as the corresponding bit lines or remain floating. Because the word line is coupled with a high voltage during the program operation, the channels of the selected cells will be turned on and pass the bit line voltages to the source lines. The source lines must be coupled to the same voltages as the bit line, or remained floating to prevent current leakage. The bias condition will program the Vt of all the four cells to +0.5V in approximately 200 us.
Continuing to refer to
FIGS. 3A and 3B
, in the second step, the word line voltage is i
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Mai Son
Saile George O.
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