Parallel bit interleaver for a wireless system

Details Parallel bit interleaver for a wireless system Parallel bit interleaver for a wireless system

2006-05-02

2010-11-09

Ha, Dac V (Department: 2611)

Pulse or digital communications

Bandwidth reduction or expansion

C375S278000, C375S285000, C375S296000, C714S756000, C341S081000

Reexamination Certificate

active

07830957

ABSTRACT:
Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.

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Giulietti, A., et al., “Parallel Turbo Coding Interleavers: Avoiding Collisions in Accesses to Storage Elements,” Electronics Letters, IEE Stevenage, GB, vol. 38, No. 5, Feb. 28, 2002, pp. 232-234, XP006018151, ISSN: 0013-5194.
International Search Report—PCT/US07/068003, International Search Authority—European Patent Office—Oct. 19, 2007.
Written Opinion—PCT/US07/068003, International Search Authority—European Patent Office—Oct. 19, 2007.

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