Parallel backplane architecture providing asymmetric bus time sl

Details Parallel backplane architecture providing asymmetric bus time sl Parallel backplane architecture providing asymmetric bus time sl

1997-03-28

2000-05-23

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Through a circuit switch

370366, 370379, H04L 1228, H04L 1250

Patent

active

06067296&

ABSTRACT:
A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit. A channel assignment memory of a bus controller is sequenced to cause data of a TDM communication channel in a selected interface unit's memory to be transferred to any memory location of another interface unit. The direction of data transfer is governed by the polarity of an edge of a clock signal conveyed over a control portion of the bus architecture.

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