Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-06-30
2004-03-02
Ghayour, Mohammad H. (Department: 2631)
Pulse or digital communications
Synchronizers
Reexamination Certificate
active
06700942
ABSTRACT:
BACKGROUND OF THE INVENTION
There is an increasing need to transport more and more data at higher and higher speeds. To overcome costs and power of using multiple cables, low-cost serializer and deserializer (SerDes) chips and chipsets have emerged, which basically time-multiplex, or serialize the parallel word, and transmit this data over a single conduit. At the receiver, the parallel word is deserialized and reassembled. Often, a coding method is incorporated in the serialization and deserialization process to insure DC balance.
Such is the case with Hewlett-Packard's GLink-LT chip set, which can transport 16 bits of parallel data above 75 MB/sec over a single conduit. The GLink-LT chip set consists of a Tx chip, which serializes the parallel word using HP's CIMT coding scheme, and an Rx chip, which deserializes and decodes the stream back to its original word. With a 4-bit coding overhead, the serial bit stream operates at bit rates above 1.5 GB/sec.
However, users have already taken advantage of the increase in throughput, and are using multiple channels of these high-speed lines. An example is to utilize 4 separate channels to transport 64 bits.
Consider the case where we have a synchronous transmission system, where we have multiple high speed serial channels from the transmitter to the receiver, and a clock brought from the receiver to the transmitter side, as shown in FIG.
1
. This type of system is often used in a remote sensing environment, where a continuous stream of data is transported back to the local site for processing. The remote site could contain multiple sensors with data converters (A/D's) and clocked with the transmitter clock. The local clock at the receiver side drives the ASIC which reads in the parallel words from the deserializers.
In this configuration, two problems in time alignment need to be overcome.
A. Unknown Recovered Data to Local Clock Phase
First, note the parallel data at the output of the deserializer is referenced off the transmitter's clock. The phase of the parallel data relative to the local clock depends on the delay times of the serial link. Thus, a system is needed to absorb the phase discrepancy of the parallel word at the deserializer, and be resynchronized to the local clock, so that it could be read in to the ASIC properly.
Although it is possible to use the recovered clocks to drive the receiver side, this clock is often jittery due to the recovering process. Also, if the link fails (i. e., cut cable), the receiver side would not have a clock. Thus, the receiver side is clocked by its own local clock.
B. Word Reassembly Uncertainty for Multiple Channel
When the parallel words at the deserializer are resynchronized to the local clock, a decision is required to advance or delay a given word if the local clock sample is near the word boundary. Since the latency delays of each channel can differ somewhat due to physical cable differences, there exists a possibility that the words from the multiple channels from differing time slots could be incorrectly reassembled.
To illustrate this, consider FIG.
2
. At the transmitter, words (a
1
-b
1
-c
1
-d
1
) and (a
2
-b
2
-c
2
-d
2
) are sent. Upon reassembly at the receiver the reassembled words are (a
1
-b
2
-c
1
-d
1
), which mixed words from different time slots.
Thus, the method which resolves the first problem (A) must not operate independently, but work collectively. A system of arbitration is needed so that a common resolution on the phase adjustment is made so that the word reassembly are not from different time slots.
III. Classical Solution:
The classical solution to synchronize the deserializer parallel output to the local clock is to feed the parallel data into a FIFO. Then the output of the FIFO is read out with the local clock. This overcomes the time boundary issue for one channel, but does not address the skew between the high speed channels.
The classical method to overcome the word reassembly problem is to use a time marker, whereby one bit of the word is reserved for a time stamp for each channel. For example, this bit only goes high for one bit over a long duration. By looking for this marker, the words from the same time slot could be reassembled with certainty.
Another method is to insert a common word across all channels at the transmitter at the same time slot. This then can be used as a time marker as the words are reassembled at the receiver ASIC. However, this requires that the continuous data must be occasionally interrupted to insert this word, thus requiring logic and memory to buffer the unsent data.
Implementing these solutions obviously takes much more extra hardware, and careful timing considerations in the ASIC designs. In addition, the time stamp bit required gives up one bit per channel.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a parallel automatic synchronization system.
In one embodiment, the parallel automatic synchronization system includes a variable delay means for receiving and variably delaying N parallel transmitted channel data words over repetitive clock cycles in response to a synchronization latch clock and for synchronously clocking out the parallel data words by a local reference clock (FREF); sync logic means for receiving repetitive control clocks corresponding to the transmitted channel data words, including a remote recovered clock (FFRM) and the local reference clock (FREF) and for generating the synchronization latch clock which determines the delay position of the variable delay of the delay means; and output latch means for clocking out the parallel data words from the variable delay means with the local reference clock (FREF).
REFERENCES:
patent: 4349832 (1982-09-01), Gallo
patent: 4821097 (1989-04-01), Robbins
Ghayour Mohammad H.
Kumar Pankaj
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