Parallel array processor interconnections

Details Parallel array processor interconnections Parallel array processor interconnections

1995-07-13

1996-11-19

Donaghue, Larry D.

Boots, shoes, and leggings

364DIG1, 3642319, 3642402, 3642213, 395309, 395286, G06F 1500

Patent

active

055772625

ABSTRACT:
Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N.times.N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. Assuming a single wire interface between PEs, there are a total of 2N.sup.2 wires in the mesh structure. Under the assumtion of SIMD operation with uni-directional message and data transfers between the processing elements in the meah, for example all PES transferring data North, it is possible to reconfigure the array by placing the symmetric processing elements together and sharing the north-south wires with the east-west wires, thereby reducing the wiring complexity in half, i.e. N.sup.2 without affecting performance. The resulting diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements. The use of Oracle for a parallel 2-D convolution mechanish for image processing and multimedia applications and for a finite difference method of solving differential equations is presented, concentrating on the computational aspects of the algorithm.

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patent: 5337395 (1994-08-01), Vassiliadis et al.
patent: 5377306 (1994-12-01), Broomhead et al.
Stewart; "Mapping Signal Processing Algorithms To Fixed Architectures"; IEEE 1988.

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