Parallel architecture for high speed flag detection and packet i

Details Parallel architecture for high speed flag detection and packet i Parallel architecture for high speed flag detection and packet i

1989-09-18

1990-11-27

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370105, 375116, H04J 324, H04L 702

Patent

active

049742230

ABSTRACT:
The present invention identifies boundaries of data packets within a serial data stream and transfers data belonging to these packets to an external device for processing or storage. Identification is accomplished at relatively high speed by parallel processing techniques using a state machine. Data may be transmitted through separate channels to a multiple channel link. This link selects one channel at a time for a predetermined period of time, and allows the data stream from the selected channel to be transmitted to the flag detector. Some of the bits in the digital data stream may be part of a flag. The flag detector generates a value corresponding to the number of bits which may correspond to a portion of a flag in the data that has entered the flag detector. Additional data from the digital data stream entering the flag detector may include the remaining bits of the flag. If so, then the detector indicates that a flag has been found. Based on the location of a flag, boundaries may be determined for data in a packet.

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William I. Fletcher, "An Engineering Approach to Digital Design", Prentice-Hall, Inc., Englewood Cliffs, N.J., pp. 335-385.

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