Parallel architecture for generating pseudo-random sequences

Details Parallel architecture for generating pseudo-random sequences Parallel architecture for generating pseudo-random sequences

1996-04-24

1998-06-02

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

377 73, 377 76, G11C 1900

Patent

active

057612650

ABSTRACT:
A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.

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