Parallel architecture error correction and conversion system

Details Parallel architecture error correction and conversion system Parallel architecture error correction and conversion system

1994-07-29

1996-12-24

Baker, Stephen M.

Excavating

371 371, 371 403, H03M 1300, G06F 1110

Patent

active

055880100

ABSTRACT:
A system and method for converting data with one error correction code format to data with a different error correction code format, including provisions for correcting the errors in the input data and checkbits. The invention reduces the levels of logic needed to accomplish the conversion. In one form, checkbits for the converted data are generated from the input data at the same time that the input data correction syndromes are generated from the input data and checkbits. Multiple sets of error pointers are then used to simultaneously correct both the converted data and the converted data checkbits.

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