Parallel analog-to-digital converter using 2.sup.(n-1) comparato

Details Parallel analog-to-digital converter using 2.sup.(n-1) comparato Parallel analog-to-digital converter using 2.sup.(n-1) comparato

1989-09-18

1990-05-22

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341160, H03M 136

Patent

active

049281038

ABSTRACT:
The invention comprises an n-bit analog-to-digital flash converter comprising 2.sup.n /2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two output, OUT and an inverted version thereof, OUT. 2.sup.n -1 consecutive latches are provided. Every other latch receives at its inputs the OUT and OUT signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the OUT signal of an adjacent input comparator. The latches having inputs coupled to the OUT and OUT signals of a single input comparator produce a comparison output which change state every two LSBs of the converter and the latches having one input coupled to the OUT signal of one input comparator and the OUT signal of an adjacent input comparator produce comparison signals which change state halfway between the output signals of the adjacent latches. Thus, a comparison output is provided for every LSB of the full scale range of the converter using only 2.sup.n /2 input comparators.

REFERENCES:
patent: 3877025 (1975-04-01), Maio
patent: 4143366 (1979-03-01), Lewis, Jr.
patent: 4591825 (1986-05-01), Bucklen
patent: 4596978 (1986-06-01), Fujita
patent: 4763106 (1988-08-01), Gulczynski

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