Coded data generation or conversion – Analog to or from digital conversion – Multiplex
Reexamination Certificate
2000-06-22
2002-05-21
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Multiplex
C341S118000
Reexamination Certificate
active
06392575
ABSTRACT:
BACKGROUND
The present invention relates to a parallel analog-to-digital converter and to a method of converting analog values to digital values in parallel, independently working processes.
In wireless communication equipment incoming signals often have to be converted to a digital shape. Also, digital signals to be issued from the equipment often have be converted to an analog shape. A schematic of a typical simple circuit used in such communication is illustrated in FIG.
1
. An analog-to-digital converter (ADC)
1
is connected to a line
5
through and delivers digital data to a signal processor
9
which communicates with user circuits, not shown, to forward information thereto. In actual embodiments the ADC has a transfer function which always includes errors. The errors result in a degraded performance in terms of the signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). In a typical application, the line
5
is connected to some device
8
for radio frequency receiving which uses an antenna
10
.
A single analog-to-digital converter can be too slow for some applications. Then, a plurality of single or individual ADCs, called ADC cells or ADC channels, are arranged which convert the successive sampled values in a cyclic process, the conversion in each cell being performed in parallel with or multiplexed in time with the conversion in the other cells, the conversion process starting at successive times for the successively sampled analog values. Such a composite device is called a parallel ADC device (PSA-ADC), see e.g. U.S. Pat. No. 5,585,796 for Christer M. Svensson et al. In
FIG. 2
such a parallel ADC device having m parallel channels is schematically illustrated. The input analog signal V
S
is sampled by successively closing switches in sample and hold circuits
11
1
,
11
2
, . . . ,
11
m
, one for each ADC
13
1
,
13
2
, . . . ,
13
m
, as controlled by clock signals from a time control unit
15
, to make the instantaneous value of V
S
to be held or stored in respective sample and hold circuit. The ADC connected to a sample and hold circuit compares the value held therein to reference values. The ADCs deliver the output words on output lines to a multiplexer
17
, from which a flow of digital words is obtained as an output of the total device. The band width of the total signal information from the composite device will thus be a multiple of the bandwidth from a single ADC channel.
In
FIG. 3
a timing diagram of the conversion process in the composite ADC device of
FIG. 2
is shown. It is observed that for each ADC there is a time period of length t
c
in which the conversion of a sampled value is executed followed by a short intermediate time period indicated at
19
, which can have a length equal to 0.
Each channel repeats the conversion process with a frequency f
c
, the conversion time t
c
thus being smaller than 1/f
c
, i.e. 1/f
c
>t
c
. The conversion frequency of the total device is then f
c,tot
=m·f
c
. In an ADC device a sufficient number of parallel cells is arranged to make this total conversion frequency as high as required. The sloping line in
FIG. 3
shows the time skew of the ADC cells, the starting times between successive cells determining the slope which is then equal to 1/(m·f
c
). If an ADC device has to have a total conversion frequency of f
c,tot
and the conversion time is t
c
for a single cell, the required number m of parallel cells is given by: m=f
c,tot
/f
c
=f
c,tot
·(1/f
c
)>f
c,tot
·t
c
and is generally selected to be the smallest integer satisfying this condition.
The cells in such a parallel ADC device always work in a predetermined successive order. Furthermore, in a parallel ADC device the individual converters will each have some characteristic or systematic errors like e.g. jitter and gain errors differing from the characteristics or systematic errors of the other converter elements, This will generate undesired tones in the output signal of the parallel ADC device such as tones having a frequency corresponding to x·f
c
±f
in
, where x is an integer and f
in
is a frequency representing an error in the individual ADC channels. These patterns will generally restrict the dynamic range of the composite ADC device.
SUMMARY
It is an object of the invention to provide a parallel ADC device having an increased dynamic range.
It is another object to provide a parallel ADC device in which the amplitude of undesired tones caused by differences of the characteristics in the element ADCs are reduced.
In a parallel ADC device a number of element converter devices are provided which work in parallel for determining digital values from analog values periodically sampled with a predetermined sampling period or sampling frequency from an input analog signal. The number of element devices and the sampling period/frequency are selected so that at each instant at least one element converter device and this is not active not performing any conversion. After the conversion is made by an element device, the next sampled value is converted by this element device or by a previously idling element device. This selecting of the next element device to perform a conversion is controlled by a choice generator providing some signal pattern. This signal pattern controls a selector which actually makes the selecting. The choice generator can provide a sequence of numbers distributed at random or a sequence having a long repetition period such as obtained from a pseudo-random generator. Also a sequence having a short period such as 0, 1, 0, 1, . . . can be used in some cases.
By controlling the choice of the next element device to make a conversion in a random way or in some systematic way having a sufficient period, the pattern in the composite output signal of the parallel ADC device comprising undesired tones is transformed to noise. The total energy of the error caused by the differences of the conversion characteristics of the element devices from each other is approximately the same as for an ADC having no idling element device but the error is distributed in the frequency domain. In some cases the noise caused by said differences can even be lower than the quantization noise.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the methods, processes, instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4345241 (1982-08-01), Takeuchi et al.
patent: 5585796 (1996-12-01), Svensson et al.
patent: 60-29028 (1998-02-01), None
Eklund, J. et al. Digital Offset Compensation of Time-Interleaved ADC using Random Chjopper Sampling, 2000 IEEE International Symposioum on Circuits and Systems (ISCAS 2000), IEEE, May 28-31, 2000, vol. 3 pp. 447-450.*
Huawen, J. et al. Time-Interleaved A/D Converter with Channel Randomization, 1997 IEEE International Symposioum on Circuits and Systems (ISCAS 1997), Jun. 9-12, 1997 vol. 1 pp. 425-428.*
Dyer, K. et al, A Comparison of Monolithic Background Calibration in Two Time-Interleaved Analog-to-Digital Converters, 1998 IEEE International Symposioum on Circuits and Systems (ISCAS '98), IEEE, May 31-Jun. 3, 1998, vol. 1, pp. 13-16.
Burns Doane Swecker & Mathis L.L.P.
Telefonaktiebolaget LM Ericsson (publ)
Williams Howard L.
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