Parallel analog to digital converter employing sample and hold s

Details Parallel analog to digital converter employing sample and hold s Parallel analog to digital converter employing sample and hold s

1988-11-25

1990-01-09

Shoop, Jr., William M.

Coded data generation or conversion

Sample and hold

341135, 341141, 341160, H03M 136

Patent

active

048931225

ABSTRACT:
A parallel analog to digital converter and a method of processing at least two independnet signals therein are disclosed in accordance with the teachings of the present invention. The analog to digital converter has an improved sample and hold stage which, in addition to quantizing the analog signals, also multiplexes them. The sample and hold stage comprises at least two differential amplifier circuits, a latch stage, and a timing stage. Each differential amplifier circuit converts one analog input by comparing it to a reference voltage. The discrete output of the differential amplifier circuit is stored in the latch stage and outputted to an encoder. The timing circuit stage first selects one differential amplifier circuit to output its discrete signal, and then selects the latch stage to output its stored results. By sequencing through each differential amplifier circuit, the present invention effectively multiplexes the analog inputs.

REFERENCES:
patent: 4147943 (1979-04-01), Peterson
patent: 4190823 (1980-02-01), Leichle
patent: 4599602 (1986-07-01), Matzuzawa et al.
patent: 4649372 (1987-03-01), Abe et al.
patent: 4677422 (1987-06-01), Naito
patent: 4739307 (1988-04-01), Marcovici et al.
Electronic Design, Vo. 29, (1981), pp. 75-79, W. K. Bucklen: "Video Digitizing Gets Extra Bit of Resolution from Flash ADC".

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