Parallel analog-to-digital converter

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307361, H03K 1317

Patent

active

042701180

ABSTRACT:
An analog signal is converted into an n bit digital signal by n comparator circuits which compare the analog input to 2.sup.n -1 reference inputs. Each comparator output alternates as the analog signal increases through the reference levels. Logic circuitry including n-1 exclusive-OR gates decodes the comparator outputs into an n bit code.
A comparator circuit for comparing the analog input signal with each of several reference levels and providing an alternating output includes a pair of differential input transistors and a current sink transistor associated with each reference level. The collectors of the differential transistor pairs are cross coupled to two output resistors which are connected to a differential exclusive-OR gate. A latching circuit is operable to latch the comparator output when the comparator is in other than the comparing mode.

REFERENCES:
patent: 2894214 (1959-07-01), Touraton
patent: 2922151 (1960-01-01), Reiling
patent: 3310688 (1967-03-01), Ditkofsky
patent: 3510681 (1970-05-01), Cooperman
patent: 3573798 (1971-04-01), Reiling
patent: 3662380 (1972-05-01), Cargile
patent: 3780317 (1973-12-01), Kurata et al.
patent: 4032797 (1977-06-01), Metcalf et al.
IBM Technical Disclosure Bulletin-Self Decoding Comparator Circuit By G. R. Woodman, Jr., vol. 9, No. 12, May 1967, pp. 1797-1798.

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