Parallel analog sampling circuit and analog-to-digital...

Details Parallel analog sampling circuit and analog-to-digital... Parallel analog sampling circuit and analog-to-digital...

1999-05-06

2001-07-10

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S094000

Reexamination Certificate

active

06259281

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to clock signal generators and, in particular, to clock signal generators that generate sub-sampling clock signals having fast and precisely-timed edges.
BACKGROUND OF THE INVENTION
In high-speed electronic circuits, it is often necessary to generate one or more clock signals from a master clock signal. Each clock signal typically has a lower frequency than the master clock signal, and may have an asymmetrical duty cycle. To prevent timing errors in the circuits that operate in response to such clock signals, the timing of the edges where the clock signal changes state must be precise, and the edges must be fast so that the change of state occurs in a time that is short compared with the cycle time of the master clock signal.
One example of an application in which multiple clock signals, called sub-sampling clock signals, are derived from a master clock signal and in which the sub-sampling clock signals are required to have fast, precisely-timed edges is high-speed analog-to-digital conversion. Analog-to-digital converters can be characterized, in part, by a maximum conversion frequency that defines the maximum frequency at which the converter can perform digital conversions of an analog input signal. The cost of analog-to-digital converters increases sharply with increasing conversion frequency. When an analog input signal has to be converted at a high conversion frequency, it is often more economical to replace a single, fast, expensive analog-to-digital converter with a parallel analog-to-digital conversion system composed of multiple slower, cheaper analog-to-digital converters arranged in parallel. Moreover, even if cost is not a factor, conversion frequencies higher than that of the fastest single analog-to-digital converter can only be obtained using a parallel analog-to-digital conversion system.
When an analog-to-digital conversion system composed of N parallel analog-to-digital converters is used to generate a digital representation of an analog input signal, the effective conversion frequency is N times the conversion frequency of the individual analog-to-digital converters.
FIG. 1
shows an example of an analog-to-digital conversion system
10
in which N=4. The analog-to-digital conversion system
10
is composed of the analog-to-digital converters
12
,
13
,
14
and
15
, each preceded by a respective track-and-hold circuit
16
,
17
,
18
and
19
, and the clock signal generator
28
that generates N sub-sampling clock signals. The analog input signal received by the analog signal input
20
is fed to the signal input of each of the track-and-hold circuits. The analog signal input of the track-and-hold circuit
16
is shown at
22
. The track-and-hold circuits each include a clock signal input. Each track-and-hold circuit receives a different one of the sub-sampling clock signals through its clock signal input. The clock signal input of the track-and-hold circuit
16
is shown at
23
.
The clock signal generator
28
derives the N sub-sampling clock signals from a master clock signal received through the master clock signal input
29
. The master clock signal runs at the conversion frequency of the analog-to-digital conversion system
10
, or at a multiple of this frequency.
The track-and-hold circuits
16
-
19
have analog signal inputs connected to the analog input
20
. For example, the analog signal input
22
of the track-and-hold circuit
16
is connected to the analog input
20
. The analog outputs of the track-and-hold circuits
16
-
19
are connected to the analog inputs of the analog-to-digital converters
12
-
15
, respectively. For example, the analog output
24
of the track-and-hold circuit
16
is connected to the analog input
25
of the analog-to-digital converter
12
. The digital outputs of the analog-to-digital converters
12
-
15
are connected to the digital output bus
27
. For example, the digital output
26
of the analog-to-digital converter
12
is connected to the digital output bus
27
.
The track-and-hold circuits
16
-
19
track the analog input signal received by the analog input
20
and sequentially hold values of the analog input signal at timings determined by the sub-sampling clock signals generated by the clock signal generator
28
. The analog-to-digital converters
12
-
15
receive the analog samples taken by the track-and-hold circuits
16
-
19
, respectively, and generate digital representations of the analog samples. The analog-to-digital converters transfer the digital representations to the digital output bus
27
to provide a serial or parallel bitstream.
The conversion frequency of the analog-to-digital conversion system
10
is equal to the frequency of the master clock signal, but each of the analog-to-digital converters
12
-
15
operates at a conversion frequency equal to 1/N of the frequency of the master clock signal. Consequently, each of the analog-to-digital converters can be simpler and less expensive than a single analog-to-digital converter that has a conversion frequency equal to the frequency of the master clock signal.
FIGS. 2A-2F
illustrate the operation of the analog-to-digital conversion system
10
shown in FIG.
1
.
FIG. 2A
shows the master clock signal received by the master clock signal input
29
.
FIGS. 2B-2E
show the sub-sampling clock signals generated by the clock signal generator
28
and fed to the clock signal inputs of the track-and-hold circuits
16
,
17
,
18
and
19
, respectively. The clock signal generator sequentially generates the N sub-sampling clock signals with a delay of at least one cycle of the master clock signal between them. Each of the sub-sampling clock signals clocks one of the track-and-hold circuits
16
-
19
at 1/N of the frequency of the master clock signal. Consequently, the sub-sampling clock signals collectively clock the track-and-hold circuits at the conversion frequency of the analog-to-digital conversion system. In the example shown, each falling edge of the master clock signal causes one of the sub-sampling clock signals to change state, and causes the sub-sampling clock signal that changed state in response to the previous falling edge to revert to its original state. The changes in state of the sub-sampling clock signals are each delayed relative to the falling edges of the master clock signal by the propagation delay t
d
of the clock signal generator.
FIG. 2F
shows the exemplary analog input signal
30
that is subject to conversion by the analog-to-digital conversion system
10
. In this example, the analog input signal is a slow linear ramp to simplify the explanation, and the track-and-hold circuits
16
-
19
hold the level of the analog input signal when the rising edge of the respective sub-sampling clock signal reaches a level half-way between its low and high states. The sub-sampling clock signals shown in
FIGS. 2B-2E
are “ideal” sub-sampling clock signals in that they all have fast edges, and they all change state at timings having a fixed relationship to the master clock signal. As a result, consecutive analog samples
31
,
32
,
33
and
34
of the analog input signal
30
captured by the track-and-hold circuits
16
-
19
, respectively, are at equal increments on the voltage scale V shown in FIG.
2
F. The analog samples are then converted to digital representations by the analog-to-digital converters
12
-
15
, respectively.
In practical embodiments of the analog-to-digital conversion system
10
, a ring counter is conventionally employed as the clock signal generator
28
. Ring counters are known in the art, and will therefore not be described in detail here. To generate N sub-sampling clock signals, a ring counter circuit composed of N counting stages is used. Although ring counters are capable of generating all of the sub-sampling clock signals with fast edges, this can only be achieved at the expense of high power consumption. Thus, in practical clock generator circuits employing a ring counter, at least some of the sub-sampling clock signals have slow edges. Moreover, th

Affiliated with

Also associated with

Rating

Parallel analog sampling circuit and analog-to-digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel analog sampling circuit and analog-to-digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel analog sampling circuit and analog-to-digital... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2544108