Coded data generation or conversion – Converter compensation
Patent
1989-10-10
1991-01-08
Shoop, Jr., William M.
Coded data generation or conversion
Converter compensation
341159, H03M 106, H03M 136
Patent
active
049839683
ABSTRACT:
The disclosure pertains to parallel analog-digital converters, the first comparator stage of which give a so-called thermometer scale, formed by a sequence of logic "ones" and logic "zeros". According to the disclosure, a corrector stage is added on in series with the comparator stage. If a comparator of the first stage accidentally gives a logic value opposite that given by the two neighboring comparators, the corrector stages forces the accidentally erroneous value to assume the same value as that the values given by the two neighboring comparators, if and only if these values are equal. The disclosed device can be applied to signal processing ADCs.
REFERENCES:
patent: 3537101 (1967-01-01), Campanella et al.
patent: 3611350 (1971-10-01), Leibowitz
patent: 4586025 (1986-04-01), Knierim
patent: 4596978 (1986-06-01), Fujita
patent: 4644322 (1987-02-01), Fujita
patent: 4712087 (1987-12-01), Traa
patent: 4884075 (1989-11-01), Mangelsdorf
patent: 4897657 (1990-01-01), Brubaker
Nguyen Truong-Thao
Thomas Francois R.
Logan Sharon D.
Shoop Jr. William M.
Thomson Composants Microondes
LandOfFree
Parallel analog-digital converter with error-correction circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel analog-digital converter with error-correction circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel analog-digital converter with error-correction circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-937514