Parallel additive scrambler and descrambler

Cryptography – Cryptanalysis

Patent

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380 33, 380 46, 380 49, 380 50, H04K 102

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053772652

ABSTRACT:
Parallel working additive scramblers produce a predetermined pseudorandom sequence of length L in a word generator, which consists of an N-stage shift register. To obtain more than N parallel located pseudorandom sequences, the word generator is connected to a network in which, in addition to the pseudorandom sequences created by modulo-2 addition, other pseudorandom sequences are created with a different phase relation. Performing the linkage operations limits the maximum bit rate sequence that can be transmitted. The entire pseudorandom sequence is stored in a memory (S). The desired pseudorandom sequence is produced in a circular storage (RS) by means of shifting operations. The circular storage (RS) is in the form of a feedback shift register (SR) and is used as the memory (S), in which each of the outputs is connected to an input of an EXOR-gate, in which a pseudorandom sequence is modulo-2 added with a partial stream of a parallelized serial data stream. The partial streams are subsequently converted to parallel-serial form in a multiplexer. Data streams with a higher bit rate sequence are possible.

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Proc. IEE, vol. 111, No. 11, Nov. 1964, pp. 1803 to 1806 by S. H. Taso, "Generation of delayed replicas of maximal-length linear binary sequences".
Siemens Research and Development, vol. 3 (1974) No. 4, pp. 218 to 224, "Erzeugung von binaren Quasi-Zufallsfolgen hoher Taktirequenz durch Multiplexen" (with English language Abstract of Introduction. K. Mohrmann).
Elektronik 26/30.12.1983, pp. 67 to 70, entitled "Parallel arbeitende Scrambler, Descrambler und Zufallsfolgen-Generatoren" with English translation of the Abstract.

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