Boots – shoes – and leggings
Patent
1991-10-09
1994-01-18
Nguyen, Long T.
Boots, shoes, and leggings
3647462, G06F 750, G06F 738
Patent
active
052804402
ABSTRACT:
A parallel adding circuit using a quinary number representation including a register having a sign bit, numeral bits and a special bit. The sign bit equal to 1 indicates positive and sign bit equal to 0 indicates negative. The numeral bits includes a first, second and third bits representing weights of 3, 2 and 1, respectively. The special bit is formed by a logical AND of an inverse (logical NOT) of said second bit and an inverse (logical NOT) of said third bit.
REFERENCES:
patent: 4620188 (1986-10-01), Sengchanh
patent: 4914614 (1990-04-01), Yamakawa
"Fast Multiplication by .+-. Quinary", Y. Sugimura, Systems Computers Controls, vol. 11, No. 5, Sep.-Oct. 1980, pp. 9-19.
".+-. Quinary Parallel Adding Circuit and Multiplication", Y. Sugimura, IEICE Transactions, vol. J71-D No. 2, Feb. 1988, pp. 193-203.
"A VLSI-Oriented High-Speed Multipler Using A Redundant Binary Addition Tree," N. Takagi, IEICE Transaction, vol. J66-D, Jun. 1983, pp. 638-690.
"A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation", N. Takagi, IEICE Transaction, vol. J67-D, Aor. 1984, pp. 450-457.
"Signed-Digit Number Representations for Fast Parallel Arithmetic", A. Avizienis, IRE Transactions on Electronic Computer, Sep. 1981, pp. 389-400.
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