Parallel adder with independent odd and even sum bit generation

Details Parallel adder with independent odd and even sum bit generation Parallel adder with independent odd and even sum bit generation

1998-04-30

2000-10-17

Ngo, Ohuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708714, G06F 750

Patent

active

061345768

ABSTRACT:
A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includes a number of selection cells that are independent of the computational cells and operate to select and output even sum bits from a number of candidate sum bits, the selection being made in accordance with predetermined ones of said recursively computed generate and propagate terms.

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Davide Dozza et al., "A 3.5 NS, 64 Bit, Carry-Lookahead Adder", Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, vol. 2, May 12-15, 1996, pp. 297-300.

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