Parallel adder-based DCT/IDCT design using cyclic convolution

Details Parallel adder-based DCT/IDCT design using cyclic convolution Parallel adder-based DCT/IDCT design using cyclic convolution

2005-03-22

2005-03-22

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S402000

Reexamination Certificate

active

06871208

ABSTRACT:
A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input values and generate opcrands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the device may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic or pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.

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