Parallel A/D converter having comparator threshold voltages defi

Details Parallel A/D converter having comparator threshold voltages defi Parallel A/D converter having comparator threshold voltages defi

1992-11-04

1994-07-05

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

341159, 307350, H03M 136

Patent

active

053271319

ABSTRACT:
A comparator includes a P-channel MOS transistor connected at the source thereof to a power source and at the drain thereof to a comparator output and the drain of an N-channel MOS transistor. The source of the N-channel MOS transistor is connected to the ground. The gates of the P-channel MOS transistor and the N-channel MOS transistor are connected to a comparator input. The logic threshold voltage of the comparator is adjusted in accordance with a circuit parameter regarding the P-channel MOS transistor and the N-channel MOS transistor such as, a gate length, a gate width or a voltage of the power source. A result of comparison by the comparator between an analog input value inputted to the comparator input and the logic threshold voltage of the comparator is outputted to the comparator output. An analog to digital converter is constructed using the comparator. The analog to digital converter is reduced in size and allows high speed analog to digital conversion.

REFERENCES:
patent: 4420743 (1983-12-01), Upadhyayula
patent: 4533903 (1985-08-01), Yamada et al.
patent: 4691189 (1987-09-01), Dingwall et al.
patent: 4845383 (1989-07-01), Iida
patent: 4872010 (1989-10-01), Larson et al.
patent: 4940981 (1990-07-01), Naylor et al.
IEEE 1991 Custom Integrated Circuits Conference, pp. 26.7.1-26.7.4 A CMOS 9 bit 25MHz 100mW ADC for Mixed Analog/Digital LSIs.
"Transistor Technics", 1990. 12, pp. 982-983.

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