Parallel A/D converter

Details Parallel A/D converter Parallel A/D converter

2003-04-18

2004-09-28

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

Reexamination Certificate

active

06798370

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a parallel A/D converter.
An A/D converter is used for converting analog input signals into digital output signals when a communication device or recording/reproducing device reproduces signals. The A/D converter outputs digital output signals encoded in response to the levels of analog input signals.
FIG. 12
illustrates a basic configuration example of a conventional 6-bit parallel A/D converter
120
. The parallel A/D converter
120
shown in
FIG. 12
is formed from a reference-voltage generation circuit
1
, a comparator section
2
and an encoder
3
.
The reference-voltage generation circuit
1
includes reference resistors r
1
to r
64
. The reference resistors r
1
to r
64
are connected in series between a node for receiving an upper-limit reference voltage V_H and a node for receiving a lower-limit reference voltage V_L. The reference-voltage generation circuit
1
outputs 2
6
reference voltages Vref
1
to Vref
64
in response to bit precision. The comparator section
2
includes 64 comparators C
1
to C
64
. The comparators C
1
to C
64
compare the magnitude of the respective reference voltages Vref
1
to Vref
64
with that of analog input signal to output a binary signal (“1” or “0”) in response to the magnitude. The encoder
3
encodes the outputs of the comparators C
1
to C
64
to output 6-bit digital output signals.
The conventional parallel A/D converter
120
is thus formed to enable analog input signals to be converted into desired digital output signals.
As described above, according to the conventional parallel A/D converter
120
, the comparators C
1
to C
64
are provided in response to the reference voltages Vref
1
to Vref
64
of which the number depends on bit precision. Accordingly, with the bit precision being increased, the number of comparators is multiplied, and the circuit scale is increased. This results in increase of power consumption.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a parallel A/D converter capable of reducing power consumption.
Specifically, a first parallel A/D converter of the present invention includes: a reference-voltage generation circuit for outputting m reference voltages (“m” is an integer of not less than two), each having different voltage values, in response to the bit precision of digital output signals; n comparators (“n” is an integer smaller than “m”); and an encoder for encoding outputs of the n comparators to output the digital output signals, wherein each of the n comparators compares the magnitude of one of the m reference voltages with that of an analog input signal.
According to the first parallel A/D converter of the present invention, the number of the comparators is n (“n” is smaller than “m”). Accordingly, compared to a conventional A/D converter, the circuit scale is reduced smaller, thereby enabling power consumption to be reduced.
Preferably, in the first parallel A/D converter of the present invention, the n reference voltages to be compared by the n comparators are symmetric with respect to a mean value of the reference voltages.
With this configuration, since the n reference voltages to be compared by the n comparators are symmetric with respect to a mean value of the reference voltages, power consumption can be reduced with the A/D conversion precision being maintained.
Preferably, in the first parallel A/D converter of the present invention, the reference-voltage generation circuit includes m reference resisters serially connected between a node for receiving an upper-limit reference voltage and a node for receiving a lower-limit reference voltage, the parallel A/D converter further includes m-n loads corresponding to m-n reference voltages, which do not correspond to the n comparators, among the m reference voltages, and each of the m-n loads is connected between a node for outputting the corresponding reference voltage and a node for receiving the analog input signal.
With this configuration, since the parallel A/D converter further includes m-n loads corresponding to m-n reference voltages, which do not correspond to the n comparators, among the m reference voltages, the linearity of reference voltage values are improved. Consequently, the A/D conversion precision can be improved.
Preferably, the first parallel A/D converter of the present invention further includes: a comparator for comparing the magnitude of any of a plurality of reference voltages and that of the analog input signal, the plurality of reference voltages appearing between one reference voltage among n reference voltages corresponding to the n comparators and a reference voltage, which is next large or small following the one reference voltage, among the n reference voltages.
With this configuration, conversion error aggravation can be mitigated even when noise and other influences take place, consequently enabling the A/D conversion precision to be improved.
Preferably, the first parallel A/D converter of the present invention further includes: p comparators corresponding to p reference voltages in response to bit precision to be secured among a plurality of reference voltages appearing between one reference voltage of n reference voltages corresponding to the n comparators and a reference voltage, which is next large or small following the one reference voltage, among the n reference voltages, wherein each of the p comparators compares the magnitude of the corresponding reference voltage with that of the analog input signal.
With this configuration, the bit precision can be secured, consequently enabling the A/D conversion precision to be improved.
Preferably, in the first parallel A/D converter of the present invention, the encoder encodes m inputs to output digital output signals, the m inputs include n inputs derived as inputs from outputs of the n comparators corresponding to the n reference voltages, and m-n inputs corresponding to m-n reference voltages, which do not correspond to the n comparators, among the m reference voltages, and each of the m-n inputs is derived as an input from an output of a comparator corresponding to a reference voltage, which is next large following a reference voltage corresponding to the input, among the n reference voltages.
With this configuration, the encoder having the same configuration as that of a conventional encoder can be used, consequently obviating the necessity of redesigning the encoder.
Preferably, in the first parallel A/D converter of the present invention, n reference voltages to be compared by the n comparators correspond to a voltage level distribution of the analog input signal.
With this configuration, the system-optimizing comparators can be set.
Preferably, in the first parallel A/D converter of the present invention, the analog input signal is a reproduction signal of a recording/reproducing device.
Preferably, in the first parallel A/D converter of the present invention, the n reference voltages to be compared by the n comparators correspond to appearance frequencies of the digital output signals.
Preferably, in the first parallel A/ID converter of the present invention, the n reference voltages to be compared by the n comparators correspond to characteristics of a communication line of a communication device that transmits the analog input signal.
A second parallel A/D converter of the present invention includes: a reference-voltage generation circuit for outputting m reference voltages (“m” is an integer of not less than two), each having different voltage values, in response to the bit precision of digital output signals; m comparators, provided in correspondence with the m reference voltages, each comparing the magnitude of the corresponding reference voltage with that of an analog input signal; n switch devices (“n” is an integer smaller than “m”), provided in correspondence with n reference voltages of the m reference voltages, each controlling the supply of the reference voltage and the analog input signal to the corresponding comparator; and an encoder for encodi

Affiliated with

Also associated with

Rating

Parallel A/D converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel A/D converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel A/D converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3210383