Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-08-06
2003-04-08
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C438S108000, C257S686000, C257S777000, C257S778000
Reexamination Certificate
active
06544815
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to chip stacks, and more particularly to a chip stack having connections routed from the bottom to the perimeter thereof to allow multiple integrated circuit chips such as BGA devices to be quickly, easily and inexpensively vertically interconnected in a volumetrically efficient manner.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. Nos. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a volumetrically efficient chip stack. In the chip stack of the present invention, connections are routed from the bottom of the chip stack to the perimeter thereof so that interconnections can be made vertically which allows multiple integrated circuit chips such as BGA, CSP, fine pitch BGA, or flip chip devices to be stacked in a manner providing the potential for significant increases in the production rate of the chip stack and resultant reductions in the cost thereof.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a chip stack comprising at least two base layers (i.e., an upper base.layer and a lower base layer). Each of the base layers includes a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the upper and lower base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. In addition to the base layers and interconnect frame, the chip stack comprises at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. The integrated circuit chip electrically connected to the first conductive pattern of the lower base layer is at least partially circumvented by the interconnect frame and at least partially covered by the upper base layer. The chip stack further preferably comprises a transposer layer which includes a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of the lower base layer is electrically connected to the third conductive pattern of the transposer layer.
In the present chip stack, the base substrate of each of the base layers defines opposed, generally planar top and bottom surfaces. The first conductive pattern itself comprises first and second sets of base pads which are disposed on the top surface of the base substrate, with the base pads of the second set being electrically connected to respective ones of the base pads of the first set via conductive traces. In addition to the first and second sets of base pads, the first conductive pattern includes a third set of base pads disposed on the bottom surface of the base substrate and electrically connected to respective ones of the base pads of the second set. More particularly, each of the base pads of the second set is preferably electrically connected to a respective one of the base pads of the third set via a base feed-through hole. The base feed-through hole is preferably plugged with a conductive material selected from the group consisting of nickel, gold, tin, silver epoxy, and combinations thereof. The integrated circuit chips are disposed upon respective ones of the top surfaces of the base substrates and electrically connected to at least some of the base pads of respective ones of the first sets. Additionally, the base pads of the second set of the lower base layer are electrically connected to the second conductive pattern of the interconnect frame, as are the base pads of the third set of the upper base layer.
The interconnect frame of the chip stack itself defines opposed, generally planar top and bottom surfaces, with the second conductive pattern comprising first and second sets of frame pads disposed on respective ones of the top and bottom surfaces. Each of the frame pads of the first set is electrically connected to a respective one of the frame pads of the second set via a frame feed-through hole which is also plugged with a conductive material preferably selected from the group consisting of nickel, gold, tin, silver epoxy, and combinations thereof. The interconnect frame is preferably disposed between the upper and lower base layers such that the frame pads of the second set are electrically connected to respective ones of the base pads of the second set of the lower base layer, with the frame pads of the first set being electrically connected to respective ones of the base pads of the third set of the upper base layer.
The transposer substrate of the present chip stack also defines opposed, generally planar top and bottom surfaces, with the third conductive pattern comprising first and second sets of transposer pads disposed on respective ones of the top and bottom surface of the transposer substrate. The transposer pads of the first set are electrically connected to respective ones of the transposer pads of the second set. Additionally, the base pads of the third set of the lower base layer are electrically connected to respective ones of the transposer pads of the first set.
In the present chip stack, the transposer pads of the first set, the frame pads of the first and second sets, and the base pads of the second and third sets are preferably arranged identical patterns. Additionally, the transposer and base substrates each preferably have a generally rectangular configuration defining opposed pairs of longitudinal and lateral peripheral edge segments. The interconnect frame itself preferably has a generally rectangular configuration defining opposed
Stetina Brunda Garred & Brucker
Vockrodt Jeff
Zarabian Amir
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