Computer graphics processing and selective visual display system – Plural display systems – Diverse systems
Patent
1993-12-28
1997-03-11
Saras, Steven
Computer graphics processing and selective visual display system
Plural display systems
Diverse systems
345 99, 345213, G09G 500
Patent
active
056106211
ABSTRACT:
A CRT controller is operated in accordance with a basic clock for a panel display and repeats a wait operation in response to a wait signal produced by a panel timing controller, which causes a compulsory synchronization with the panel timing. A 1/2 frame buffer is also provided. Display data supplied by the CRT controller and display data read from the 1/2 frame buffer are alternately selected such that data is supplied in an order conforming to the panel display of a double screen type panel display. A display of the double screen type panel display is controlled in accordance with an application program directed to a CRT display without modifying the order of the display data produced by the CRT controller and without changing the timing data which has been set in the CRT controller. The 1/2 frame buffer may be a general-purpose memory which stores 1/2 frame and one line of the panel display data. A 1/2 frame buffer control circuit shifts a writing address of the 1/2 frame buffer by one line in a reverse direction to a direction of scanning for writing at the beginning of each new frame.
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Itoh Shuhei
Kurata Mitsuhiro
Saras Steven
Yamaha Corporation
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