Pairing of spills for parallel registers

Details Pairing of spills for parallel registers Pairing of spills for parallel registers

2004-01-23

2008-08-26

Vu, Tuan Anh (Department: 2193)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

Reexamination Certificate

active

07418698

ABSTRACT:
Embodiments of the present invention provide a design for handling register overflow in a CPU having parallel registers. In an embodiment, spill code generated by a registers allocator may be analyzed to identify register spill instructions that can be associated. Register spill instructions that can be associated may be rewritten as parallel spill instructions, and the corresponding register spills may be configured for storage into memory in a manner permitting them to be loaded back to the registers in parallel.

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