Paired instruction processor precise exception handling mechanis

Details Paired instruction processor precise exception handling mechanis Paired instruction processor precise exception handling mechanis

1989-05-24

1991-12-24

Lee, Thomas C.

Excavating

371 161, 3642653, 3642318, 3642563, 3642656, G60F 1100, G60F 938

Patent

active

050758446

ABSTRACT:
A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

REFERENCES:
patent: 4500959 (1985-02-01), Kubo et al.
patent: 4710866 (1987-12-01), Zolnowsky et al.
patent: 4782441 (1988-11-01), Inagami et al.
patent: 4956770 (1990-09-01), Johnson et al.
patent: 4985825 (1991-01-01), Webb, Jr. et al.

Affiliated with

Also associated with

Rating

Paired instruction processor precise exception handling mechanis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Paired instruction processor precise exception handling mechanis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Paired instruction processor precise exception handling mechanis will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-49020