Paging system using extension tables for conflict resolution

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395600, G06F 1200, G06F 1210, G06F 1540

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active

052935957

ABSTRACT:
A method of resolving conflicts when the index values of different binary bit designators are found to be equal is provided which is implementable in a virtual memory to real memory address translation scheme and alternately in a data base environment. Binary bit designators are used, each of which consists of a first compare segment, a second index segment and a third offset segment. When two indexes are found to be identical, similar groups of bits in the first segment are considered as subsidiary indexes and are utilized in sequence until all of the bits of said first segments have been used. Each time an index operation occurs a new table entry in a new table is identified, until a group of bits from the first segments of the different binary bit designators are found to be unequal. When this occurs, comparisons of the final table entries in the final table are undertaken to determine if each stored value in each final table entry is equal to the value represented by the associated first segment.

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Thakkar et al., "Virtual Address Translation Using Parallel Hashing Hardware," pp. 701-702.

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