Paging receiver having a noise-immune verification circuit for d

Details Paging receiver having a noise-immune verification circuit for d Paging receiver having a noise-immune verification circuit for d

1987-06-17

1989-06-06

Griffin, Robert L.

Telecommunications

Receiver or analog modulated signal frequency converter

With particular receiver circuit

34082544, H04B 116, H04Q 914

Patent

active

048378542

ABSTRACT:
A selective calling radio paging receiver includes a battery saving controller which activates the high power drain unit of the receiver at periodic intervals for allowing the detection of a preamble contained in a received digital paging signal and deactivates it for a period longer than the period of activation for power savings purposes. The power saving is disabled in response to the detection of a preamble for continued power activation to permit a sync detector and an address detector to be operated in succession. A window pulse is generated in synchronism with the clock timing of the received digital signal so that its binary level transition is time coincident with each window pulse. If noise occurs in the received signal, binary level transitions occurs which are out of coincidence with window pulses. The time-coincident binary level transitions and the noncoincident binary level transitions are counted to give first and second counts, respectively. If a valid preamble is lost or corrupted and if the first count is greater than the second, a valid indication of the received signal will be given and power activation is continued to operate the sync and address detectors in succession.

REFERENCES:
patent: 4353065 (1982-10-01), Mori
patent: 4419765 (1983-12-01), Wykoff et al.
patent: 4506386 (1985-03-01), Ichikawa et al.
patent: 4523332 (1985-06-01), Mori
patent: 4652875 (1987-03-01), Waki

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