Pager receiver having a common timer circuit for both sequential

Details Pager receiver having a common timer circuit for both sequential Pager receiver having a common timer circuit for both sequential

1989-01-30

1990-05-22

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

340825520, 455 58, H04Q 702, H04B 700

Patent

active

049280864

ABSTRACT:
A pager receiver includes at least one lock-out circuit, an out-of range circuit, and a single timer coupled to the lock-out and out-of range circuits and responsive to timing signals generated by the pager for generating an initiated one of either the lock-out timer interval or out-of range time interval. Each lock-out circuit of the pager receiver corresponds to an address function programmed therein and is activated by the function detect signal generated in response to the initial decoding of the corresponding address function to initiate the generation of the lock-out time interval by the single timer and to inhibit the corresponding alert annunciation from responding to subsequently generated function detect signals corresponding thereto for the duration of the lock-out time interval. The single timer is also initiated to generate the out-of-range time interval at the generation of each sync pulse timing signal by the pager receiver, but only in the absence of an activated lock-out circuit. Accordingly, the single timer is disabled from initiating the generation of the out-of-range time interval for the duration of an initiated lock-out time interval. Still further, the single timer may be reinitiated to generate the lock-out time interval during the generation of a lock-out time interval by an activated lock-out circuit corresponding to an uninhibited alert annunciation.

REFERENCES:
patent: 4663623 (1987-05-01), Lax et al.
patent: 4682165 (1987-07-01), Danis
patent: 4837854 (1989-06-01), Oyagi et al.
patent: 4839628 (1989-06-01), Davis et al.

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