Paged memory management unit which locks translators in translat

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G06F 1210

Patent

active

047274859

ABSTRACT:
In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed from page descriptors comprising, in part, translation tables stored in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in a lock field of the page descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.

REFERENCES:
patent: 3970999 (1976-07-01), Elward
patent: 4038645 (1977-07-01), Birney et al.
patent: 4084226 (1978-04-01), Anderson et al.
patent: 4084230 (1978-04-01), Matick
patent: 4638426 (1987-01-01), Chang et al.

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