Paged memory management unit having variable number of translati

Details Paged memory management unit having variable number of translati Paged memory management unit having variable number of translati

1985-04-01

1988-08-09

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1208

Patent

active

047632500

ABSTRACT:
In a paged memory management unit (PMMU), a translation control (TC) register contains a set of table indexes which define the number of bits of the logical address to be used to access the translation table at the respective levels. The TC register also contains an initial shift field which defines the number of high order bits of the logical address to be discarded before an address translation, and a page size field which defines the number of low order bits of the logical address comprising the page address. Each descriptor in each translation table contains a descriptor type field which defines whether that particular descriptor is a translation descriptor or a pointer descriptor. If a pointer descriptor is encountered at a table level other than the lowest level, the translation table walk is terminated early and the translation performed using that pointer descriptor. In general, a table may occupy either the lower or upper portions of the page in which such table is stored. Each descriptor contains a lower/upper (L/U) bit which defines the relative displacement of the next-lower table relative to the specified table address. If a table is addressed outside the appropriate range, the PMMU will not abort the table walk and bus error the access.

REFERENCES:
patent: 3657705 (1972-04-01), Mekota, Jr. et al.
patent: 4128875 (1978-12-01), Thurber et al.
patent: 4615006 (1986-09-01), Hirano
Poppendieck, M. and Desautels, E. J., "Memory Extension Techniques for Minicomputers", in Computer, May 1977, pp. 68-75.
Olbert, A. G., "Single Level Address Translation", IBM Technical Disclosure Bulletin, vol. 20, No. 1, pp. 108-109.

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