Paged memory controller

Details Paged memory controller Paged memory controller

1992-12-30

1994-04-12

Bowler, Alyssa H.

Boots, shoes, and leggings

395400, 3642384, 364DIG1, 3642402, 36424341, G06F 1200, G06F 1300

Patent

active

053033647

ABSTRACT:
A computer system has a processor coupled to a cache controller, uses page mode memory devices and performs page hit detection on the processor local bus. Column address and data values are latched by a memory controller on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

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