Page-write indicator for non-volatile memory

Details Page-write indicator for non-volatile memory Page-write indicator for non-volatile memory

1998-01-20

1999-09-28

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

365236, 3652385, G11C 1604

Patent

active

059598867

ABSTRACT:
A circuit for activating page-write operations in a floating-gate memory includes a first and a second time lag circuit. A resetting signal resets a first time lag whenever a word is written in a buffer of the memory. The first time lag circuit provides a state bit indicating that the first time lag has ended or not ended. The second time lag circuit activates a second time lag at the end of the first time lag and the end of the second time lag activates the writing of the page in the memory. The invention also relates to a method of writing in memory that uses a first and a second time lag.

REFERENCES:
patent: 5742543 (1998-04-01), Fazio
patent: 5754469 (1998-05-01), Hung et al.
A Million-Cycle CMOS 256K EEPROM, Dumitru Cioaca et al., IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 5, 1987, pp. 684-692.
EEPROM Standards and Reliability: An Interim Report, Richard Orlando, EDN Electrical Design News, vol. 30, No. 1, Jan. 10, 1985, pp. 159-174.

Affiliated with

Also associated with

Rating

Page-write indicator for non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Page-write indicator for non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Page-write indicator for non-volatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-711132