Page-mode type memory writing control circuit using end-of-page

Details Page-mode type memory writing control circuit using end-of-page Page-mode type memory writing control circuit using end-of-page

1992-10-06

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Byte or page addressing

36523008, G11C 800

Patent

active

053273958

ABSTRACT:
A NOR operation is performed on the address bit by bit by a NOR circuit, and when the final address in a page is detected from the result of the NOR operation by a final address detection circuit, a program starting circuit executes data writing to a memory cell. This can ensure detection of the final address in a page without using a counter circuit. It is therefore possible to simplify the structure of the final address detection circuit and reduce the circuit area occupying in a semiconductor memory device.

REFERENCES:
patent: 4378594 (1983-03-01), Kenyon
patent: 4636986 (1987-01-01), Pinkham
patent: 4644494 (1987-02-01), Muller
patent: 4686650 (1987-08-01), Hori et al.
patent: 4870622 (1989-09-01), Aria et al.
patent: 4961171 (1990-10-01), Pinkham et al.
"64-bit EEPROM Speeds In-System Reprogramming, Adds Data Polling", Electronic Design, Aug. 23, 1984, pp. 197-204.
Toshiba Corporation, "4M bit CMOS NAND E.sup.2 PROM TC584000P/F/FT/TR Target Specification," FT-001A Sep., 1991.

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