Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-10-01
1998-11-10
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518512, 36518529, G11C 1606
Patent
active
058354140
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit memory devices based on floating gate transistor technology; and more particularly to high speed program, program verify, read and erase verify algorithms for page mode flash memory.
2. Description of Related Art
Flash memory is a growing class of non-volatile storage integrated circuit based on floating gate transistors. The memory cells in a flash device are formed using so called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate of the transistor by a second layer of insulating material.
To store data in a floating gate memory cell, the floating gate is charged or discharged using a Fowler-Nordheim tunneling mechanism, or a hot electron injection mechanism. The Fowler-Nordheim tunneling mechanism is executed by establishing a large positive (or negative) voltage between the gate and source or drain of the device. This causes electrons to be injected into (or out of) the floating gate through the thin insulator. The hot electron injection mechanism is based on an avalanche process. Hot electron injection is induced by applying potentials to induce high energy electrons in the channel of the cell, which are injected across the thin insulator into the floating gate. To induce hot electron injection, a potential is applied across the source and drain of the device, along with a positive potential on the control gate. The positive potential on the control gate tends to draw electrons from the current in the channel of the device into the floating gate.
The acts of charging and discharging the floating gate in a floating gate memory device are relatively slow compared to writing other memory types, like static or dynamic random access memory, and limit the speed with which data may be written into the device.
Another problem associated with floating gate memory devices arises because the charging and discharging of the floating gate is difficult to control over a large array of cells. Thus, some of the cells program or erase more quickly than others in the same device. In a given program or erase operation, not all the cells subject of the operation will settle with the same amount of charge stored in the floating gate. Thus, so called program verify and erase verify sequences have been developed to efficiently ensure that the memory is being accurately programmed and erased. The program and erase verify operations are based on comparing the data stored in the floating gate memory array with the intended data. The process of comparing data is relatively time consuming, involving sequencing byte by byte through the programmed or erased cells. If a failure is detected in the verify sequence, then the program or erase operation is retried. Program retries are typically executed word-by-word or byte-by-byte in prior art devices. Thus, bits successfully programmed in a byte with one failed bit are subject to the program cycle repeatedly. This can result in over-programming and failure of the cell.
One approach to resolving this issue is set forth in U.S. Pat. No. 5,163,021 by Mehrotra, et al., at column 19, line 10 at sec. FIGS. 14-17.
To improve the efficiency of program and program verify operations, so called page mode flash devices have been developed. In these devices, a page buffer is associated with the memory array. The page buffer includes a set of bit latches, one bit latch associated with each global bit line in the array. To program a page in the array, the page buffer is loaded with the data to be programmed, by transferring byte by byte the program data into the bit latches of the page buffer. The program operation is then executed in parallel on a bit line by bit line basis controlled by the contents of the bit latches. The ve
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Hung Chun-Hsiung
Lee Yu-Sui
Wan Ray-Lin
Ho Hoai V.
Macronix International Co. Ltd.
Nelms David C.
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