Page mode operation of main system memory in a medium scale comp

Details Page mode operation of main system memory in a medium scale comp Page mode operation of main system memory in a medium scale comp

1985-09-23

1989-04-18

Moffitt, James W.

Static information storage and retrieval

Addressing

365193, 365194, G11C 800

Patent

active

048233242

ABSTRACT:
A memory device is disclosed which is comprised of a plurality of memory boards each having at least one memory bank associated therewith with each memory bank including a plurality of memory elements addressable by rows and columns. In page-mode operation of the memory device, all of the memory elements receive the active row address strobe signal RAS. The RAS signal is maintained active as long as the memory is to remain in page-mode operation. Memory address information is decoded to select a memory board and a memory bank from the plurality of memory boards and to enable the memory elements to permit either a read or a write operation without the need for performing additional address strobe cycles.

REFERENCES:
patent: 4486860 (1984-12-01), Takemae et al.
patent: 4541090 (1985-09-01), Shiragasawa
patent: 4575825 (1986-03-01), Ozaki et al.
patent: 4694454 (1987-09-01), Matsuura

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