Page mode memory system

Details Page mode memory system Page mode memory system

1983-06-03

1985-02-19

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 930

Patent

active

045009619

ABSTRACT:
A multi-page ROM uses programmable pointers for selection of a page. The pointers each have a preliminary latch circuit, an output latch circuit, and a delay circuit. The preliminary latch circuit receives and stores program address signals when a first signal is present. The output latch receives the address stored in the preliminary latch when a second signal is present. The delay circuit removes the first signal before the second signal is present and delays the presence of the first signal for a delay period following the removal of the second signal.

REFERENCES:
patent: 3737860 (1973-06-01), Sporer
patent: 4037214 (1977-07-01), Birney et al.
patent: 4118773 (1978-10-01), Raguin et al.
patent: 4158227 (1979-06-01), Baxter et al.
patent: 4240142 (1980-12-01), Blahut et al.
patent: 4374417 (1983-02-01), Bradley et al.

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