Static information storage and retrieval – Floating gate – Multiple values
Patent
1996-10-01
1998-05-19
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Multiple values
36518512, 36518522, G11C 1134
Patent
active
057544697
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit memory devices based on floating gate transistor technology; and more particularly to high speed page mode flash memory in which multiple bits of data are stored in each cell.
2. Description of Related Art
Flash memory is a growing class of non-volatile storage integrated circuit based on floating gate transistors. The memory cells in a flash device are formed using so called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate of the transistor by a second layer of insulating material. To store multiple bits in a single floating gate transistor, it is known to charge or discharge the floating gate to a plurality of predefined levels. The plurality of predefined levels establish different threshold voltages for the floating gate transistor, so the level to which the transistor is programmed may be readily sensed. See, U.S. Pat. No. 4,054,864 entitled METHOD AND DEVICE FOR THE STORAGE OF ANALOG SIGNALS by Audaire, et al., issued 18 Oct. 1977; U.S. Pat. No. 4,890,259 entitled HIGH DENSITY INTEGRATED CIRCUIT ANALOG SIGNAL RECORDING AND PLAYBACK SYSTEM by Simko, issued 26 Dec. 1989; U.S. Pat. No. 5,163,021 entitled MULTI-STATE EEPROM READ AND WRITE CIRCUITS AND TECHNIQUES by Mehrotra, et al., issued 10 Nov. 1992; U.S. Pat. No. 5,218,569 entitled ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY WITH N-BITS PER MEMORY CELL by Banks, issued 8 Jun. 1993; U.S. Pat. No. 5,294,819 entitled SINGLE-TRANSISTOR CELL EEPROM ARRAY FOR ANALOG OR DIGITAL STORAGE by Simko, issued 15 Mar. 1994; U.S. Pat. No. 5,418,743 entitled METHOD OF WRITING INTO NON-VOLATILE SEMICONDUCTOR MEMORY by Tomioka, et al., issued 23 May 1995; U.S. Pat. No. 5,422,845 entitled METHOD AND DEVICE FOR IMPROVED PROGRAMMING THRESHOLD VOLTAGE DISTRIBUTION IN ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY ARRAY by Ong, issued 6 Jun. 1995; U.S. Pat. No. 5,450,363 entitled GRAY CODING FOR A MULTILEVEL CELL MEMORY SYSTEM by Christopherson, et al., issued 12 Sep. 1995; International Publication Number WO 95/34074 entitled DYNAMIC SINGLE TO MULTIPLE BIT PER CELL MEMORY by Intel Corporation, published 14 Dec. 1995; International Publication Number WO 95/34075 entitled SENSING SCHEMES FOR FLASH MEMORY WITH MULTILEVEL CELLS by Intel Corporation, published 14 Dec. 1995; Bauer, et al., "A Multilevel-Cell 32 Mb Flash Memory", 1995 IEEE international Solid-State Circuits Conference, pg. 132-133 (Feb. 16, 1995); and Jung, et al., "A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications", 1996 IEEE International Solid-State Circuits Conference, pg. 32-33 (Feb. 8, 1996).
The prior art multi-level floating gate memory systems typically provide for byte-by-byte programming algorithms, and require sense amplifiers capable of detecting multiple levels of conduction in the floating gate memory devices being sensed. Thus, the multi-level flash or floating gate memory devices of the prior art are limited in speed by the byte-by-byte programming and sensing algorithms, and require complex sense amplifier circuitry.
To store data in a floating gate memory cell, the floating gate is charged or discharged using a Fowler-Nordheim tunneling mechanism, or a hot electron injection mechanism. The Fowler-Nordheim tunneling mechanism is executed by establishing a large positive (or negative) voltage between the gate and source or drain of the device. This causes electrons to be injected into (or out of) the floating gate through the thin insulator. The hot electron injection mechanism is based on an avalanche process. Hot electron injection is induced by applying potentials to induce high energy electrons in the channel of the cell, which are injected across the thin insulator into the floating gate. To induce
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Cheng Yao-Wu
Hung Chun-Hsiung
Wan Ray-Lin
Macronix International Co. Ltd.
Popek Joseph A.
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