Page mode erase in a flash memory array

Details Page mode erase in a flash memory array Page mode erase in a flash memory array

1998-03-13

2000-09-12

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

36518512, 36518533, 36518518, G11C 1604

Patent

active

061187054

ABSTRACT:
In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately -10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.

REFERENCES:
patent: 5270980 (1993-12-01), Pathak et al.
patent: 5406521 (1995-04-01), Hara
Kynett, et al., "A 90ns 100K Erase/Program Cycle Megabit Flash Memory", Session 10., Nonvolatile Memories, IEEE Internaional Solid-State Circuits Conferences, Feb. 16, 1989, pp. 140-141.
Venkatesh, et al., "TP 2.7: A 55ns 0.35pm 5V-only 16M Flash Memory with Deep-Power-Down", ISSCC96/Session 2/Flash Memory/Paper TP 2.7, 1996 IEEE Internaitonal Solid-State Circuits Conference, pp. 44-45.

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