Page mode comparator decode logic for variable size DRAM types a

Details Page mode comparator decode logic for variable size DRAM types a Page mode comparator decode logic for variable size DRAM types a

1991-02-22

1994-04-05

Dixon, Joseph L.

G06F 1200

Patent

active

053012925

ABSTRACT:
Apparatus for decoding and comparing memory addresses which determines DRAM size and interleave options utilized is disclosed. A row address and bank select bits are decoded and latched and are subsequently compared with the address during the next memory cycle. If the next address matches the address stored in the latch, a "page hit" occurs and the memory cycle is shortened since the addresses during the consecutive memory address will differ only in the column address.

REFERENCES:
patent: 4803621 (1989-02-01), Kelly
patent: 4809234 (1989-02-01), Kuwashiro
patent: 4924375 (1990-05-01), Fung et al.
patent: 5051889 (1991-09-01), Fung et al.

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