Page mode and nibble mode DRAM

Details Page mode and nibble mode DRAM Page mode and nibble mode DRAM

1996-04-01

1996-12-24

Cunningham, Terry

Static information storage and retrieval

Addressing

Byte or page addressing

365221, 365236, G11C 700

Patent

active

055879640

ABSTRACT:
A page mode
ibble mode dynamic random access memory (DRAM) comprising row and column decoders, the column decoder further comprising a column address buffer and a column address buffer counter. The page mode
ibble mode DRAM also comprises a buffer controller means adapted to receive a write enable signal and to determine whether the DRAM should be placed in a page mode or a nibble mode to facilitate the particular memory access requested by a memory controller. An asserted write enable signal, may indicate, for example, a write operation, thereby calling for the page mode
ibble mode DRAM to move into a page mode to effectuate the write operation. The page mode
ibble mode DRAM also utilizes the write enable signal in the conventional manner, to indicate the initiation of a particular type of memory access, namely a write operation or a read operation.

REFERENCES:
patent: 4575825 (1986-03-01), Ozaki et al.
patent: 4586167 (1986-04-01), Fujishima et al.
patent: 4672582 (1987-06-01), Nishimura et al.
patent: 4833650 (1989-05-01), Hirayama et al.
patent: 4876671 (1989-10-01), Norwood et al.
patent: 5088062 (1992-02-01), Shikata

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