Page memory device capable of short cycle access of different pa

Details Page memory device capable of short cycle access of different pa Page memory device capable of short cycle access of different pa

1994-09-19

1996-06-25

Chan, Eddie P.

Boots, shoes, and leggings

395474, 395432, 364DIG1, 3642281, 364249, 3642543, 36518905, 36523002, 3652385, G06F 1200, G06F 1316, G11C 700, G11C 800

Patent

active

055309550

ABSTRACT:
A plurality of data latch circuits each used to store row data for one page from a memory cell array are provided, each data latch circuit being allotted to a data processor. An address is given in a multiplexed manner of a row address RA and a column address CA. Data in each data latch circuit is updated when the row address RA is given while the data latch circuit is selected.

REFERENCES:
patent: 4829471 (1989-05-01), Banerjee et al.
patent: 4939636 (1990-07-01), Nakagawa et al.
patent: 5088062 (1992-02-01), Shikata
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5278790 (1994-01-01), Kanabara
patent: 5283880 (1994-02-01), Marcias-Gorza
patent: 5293347 (1994-03-01), Ogawa

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