Page interleaved memory access

Details Page interleaved memory access Page interleaved memory access

1987-10-23

1990-05-08

Shaw, Gareth D.

Boots, shoes, and leggings

3642436, 364243, 3642461, 3642464, G06F 100

Patent

active

049243756

ABSTRACT:
The present invention provides a memory organization scheme for a high-performance memory controller. The memory organization of the present invention combines page mode techniques and interleaving techniques to achieve high-performance.
Sequential pages of memory are interleaved between memory banks so that memory accesses which are a page apart will be to two different memory banks. A page is preferably defined by a single row, with 2K columns per row defining the number of bits in a page. Accesses to bits in the same page as a previous access omit the row pre-charge cycle, thus speeding up the memory cycle. Accesses to a separate bank of memory chips from the previous access are likewise speeded up since there is no need to wait for the completion of the cycle in the previous bank before initiating the cycle in the separate bank.

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