Page controlled cache directory addressing

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G06F 1300

Patent

active

044411553

ABSTRACT:
The described embodiment modifies cache addressing in order to decrease the cache miss rate based on a statistical observation that the lowest and highest locations in pages in main storage page frames are usually accessed at a higher frequency than intermediate locations in the pages. Cache class addressing controls are modified to change the distribution of cache contained data more uniformly among the congruence classes in the cache (by comparison with conventional cache class distribution). The cache addressing controls change the congruence class address as a function of the state of a higher-order bit or field in any CPU requested address.

REFERENCES:
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 3848234 (1974-11-01), MacDonald
patent: 4010451 (1977-03-01), Kibble et al.
patent: 4228503 (1980-10-01), Waite et al.
patent: 4314331 (1982-02-01), Porter et al.
patent: 4363095 (1982-12-01), Woods et al.

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